PLL frequency synthesizer with lock detection circuit
US6757349B1 · kind B1 · utility
14Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL frequency synthesizer including a lock detection circuit which detects whether or not the PLL is locked. First and second phase difference signals are generated from a reference signal and a compared signal by a phase comparator. The lock detection circuit determines the locked condition and generates a clock detection signal using only the first and second phase difference signals and does not require an external clock signal. The lock detection signal is generated independently of the frequencies of the reference signal and the compared signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.