Image processing architecture
US6757430B2 · kind B2 · utility
5Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V30/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a central processing unit, a bus and circuit. The central processing unit is coupled to the bus and segments an image into at least one text region and at least one graphics region. At least one of the circuit modules is associated with the processing of the text region(s), and at least one of the circuit modules is associated with the processing of the graphics region(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.