Multi-processor architecture for parallel signal and image processing
US6757761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2001 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Sep 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.