Multi-mode processor bus bridge
US6757762B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor bus bridge includes a buffer space disposed between a first bus and a second bus. The first bus is operated in a first mode by a first processor and the second bus is operated in a second mode by a second processor. The first bus has an electrical structure which is different from the electrical structure of the second bus. The first mode may also differ from the second mode. The processor bus bridge has a protocol logic module disposed between the first processor and the second processor for controlling data transfer across the buffer space in the first and second modes. Thus, the bus bridge enables communications between dissimilar processor buses while increasing performance and reducing CPU overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.