Apparatus and method for efficiently sharing memory bandwidth in a network processor
US6757795B2 · kind B2 · utility
9Cited by
16References
31Claims
0Family size
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Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.