Exposed and embedded overlay structure
US6759112B2 · kind B2 · utility
10Cited by
4References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2000 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.