Method for plasma etching a microelectronic topography using a pulse bias power
US6759339B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Dec 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.