Data latch circuit having anti-fuse elements
US6759895B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data latch circuit includes anti-fuse elements for storing remedy information therein as to replacement of defective memory cells by redundant memory cells. For programming the anti-fuse elements to a logic level “1” in a programming mode, control signals CTL1 and CTL2 are set at a low level and a high level, respectively, and programming control signals PGMA and PGMB are set at a high level and a low level, respectively. A voltage selection node Nvs delivers a programming voltage Vpp, lowering an output terminal RCB to effect dielectric breakdown of anti-fuse element 25, which assumes a low resistance. In a normal operation mode, programming voltages PUMA and PGMB are set at a low level and a high level, respectively, and both control signals CTL1 and CTL2 are set at a low level Voltage output node Nvs delivers the normal operating voltage, raising output terminal RC to a high level to thereby deliver the stored logic level “1”.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.