Method and apparatus for block-based chip timing estimation in a code division multiple access communication system
US6760321B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Oct 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7117
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A code division multiple access communication system receiver includes block-based chip timing estimation. A chip timing estimate is generated from samples of a received signal by performing an averaging operation over a designated block of chips in each of first and second legs of an early-late synchronizer. The chip timing estimate is determined as a function of an error signal corresponding to the difference between outputs of the first and second legs, and is utilized to adjust a code generator clock or to otherwise control chip timing in the receiver. In an illustrative embodiment, a separate block-based chip timing estimator is implemented in each of the fingers of a Rake receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.