Device for timing reconstruction of a data channel transported on a packet network and its process
US6760395B1 · kind B1 · utility
2Cited by
8References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2000 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jul 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0632
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A memory for data accumulation includes an input on which such data are entered as a stream of input data under the control of an input timing signal and an output starting from which the data entered in memory are read as a stream of output data under the control of a reconstructed timing signal. A phase-locked loop uses this input timing signal as an input signal to generate a corresponding phase-locked output signal. Of such phase-locked loop output. A device is provided to measure residual phase wander and act on the transfer function band of the phase of phase-locked loop output which is preferably without ring filters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.