Gateword acquisition in a multiprocessor write-into-cache environment
US6760811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a “set gate control flag” command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor. Optionally, the processor so acquiring ownership broadcasts a “reset gate control flag” command to all processors when it has acquired ownership of the gate control word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.