Modulo addressing
US6760830B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jul 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+M<B, a second corrected target module address when I+M>=B+L and an uncorrected module address when B<=I+M<B+L.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.