Algorithm for resynchronizing a bit-sliced crossbar
US6760870B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/557
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data switch is configured to communicate data messages in the form of multibit data unit segmented into a plurality of multibit data subunits. The data switch includes at least two separate, parallel switching units, each having a plurality of ports to communicate the multibit data subunits. Hardwired or software implemented prioritization logic provides for the initiations of transfer of data messages between the ports in response to a category of the data messages. A memory is used to store a history of prior data message transfers so that least recently transferred message types are serviced prior to those most recently switched. So as to reestablish synchronization between the parallel switching units, such as loss of a data subunit, a controller responds to a reset condition by temporarily suspending communications between affected ones of the ports and clearing the history so to recommence lock-step operations of the units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.