Configurable and memory architecture independent memory built-in self test
US6760872B2 · kind B2 · utility
9Cited by
8References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jun 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.