Scalar product and parity check
US6760880B1 · kind B1 · utility
10Cited by
15References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of AND gates each to receive as input a bit of a first binary vector and a corresponding bit of a second binary vector, where the length of the first binary vector is not greater than the length of the second binary vector. The apparatus also includes a multiple input XOR gate to calculate in a single cycle a scalar product of the first binary vector and the second binary vector by performing an exclusive OR operation on the output of each of the AND gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.