Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)
US6760881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jan 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.