Method of forming an interlayer dielectric film
US6762126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jul 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02282
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for forming an interlayer dielectric film, an insulating film is deposited on a semiconductor substrate that has a metal wiring pattern. The insulating film is polished by CMP until exposing an upper portion of the wiring pattern. A spin on glass composition, which includes polysilazane, is coated over the polished insulating material and exposed portions of the wiring pattern to form a film. The film is then pre-baked in a temperature range of 50 to 350° C., and then hard-baked in a temperature range of 300 to 500° C. After the hard-baking, the film is then heat-treated in an oxidation atmosphere. With the hard-baking, gasses of the coating of film may be removed so that the amount of gas generated during a subsequent anneal or heat-treating process may be reduced. Accordingly, particle contaminants may be reduced by such process in addition to providing a means for reduced risk of crack formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.