Stack arrangements of chips and interconnecting members
US6762487B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Apr 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structures for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One aspect is a stack of two chips with a preformed interconnecting support connecting the two chips and with space for mounting a third chip to at least one of the other two chips in an interstitial space between the two chips and inside the support. Another aspect is a chip stack where two smaller chips are interconnected a larger third chip on both sides thereof and further with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another aspect is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.