Internal circuit structure of semiconductor chip with array-type bonding pads and method of fabricating the same
US6762507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | May 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.