Lock detection circuit for a phase locked loop circuit
US6762631B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2001 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Nov 18, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock detection circuit is disclosed that is capable of detecting when a phase locked loop circuit is in a locked or unlocked condition. The invention comprises an exclusive OR gate, a deglitch unit, a gate circuit, a count lock circuit, a count unlock circuit, and a flip flop circuit. The deglitch unit outputs a clear “clr” signal only when UP signals and DN signals from a phase frequency detector in the phase locked loop circuit are mismatched in time by more than a predetermined period of time. Detection of a locked condition or an unlocked condition is made by processing “clr” signals in the count lock circuit and in the count unlock circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.