Dual-loop PLL with DAC offset for frequency shift while maintaining input tracking
US6762634B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Aug 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When the DAC offset occurs, the voltage to the VCO and the frequency of the primary loop change and the primary loop loses tracking of the reference clock. The secondary loop keeps tracking the reference clock during the DAC offset while the primary loop is open. Then the output clock of the secondary loop is applied as the feedback clock to the phase comparator of the primary loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.