Bi-directional capable bucket brigade circuit
US6762795B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2000 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/768
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A time delay integration circuit in which a number of unit cell inputs (101, 103, 105, 107) along with their respective switches (170, 171, 172, 173) are input to a bi-directional BBD circuit (110). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs (111, 112; 113, 114; 115, 116; 117, 118; 119, 120; 121, 122; 123, 124; 125, 126; 127, 128; 129, 130; 131, 132; 133, 134; 135, 136; 137, 138; 139, 140; 141, 142) connected in series and numerous storage capacitors (151, 152,153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases Ø1 and Ø2. The gates of the MOSFETs in each pair are separated from the clock phases Ø1 and Ø2 and function respectively as screen gate and transfer clock for one direction of charge flow, and as transfer clock and screen gate for the other direction of charge flow. Transfer direction is changed by switching which MOSFET in a pair becomes clocked a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.