Data coherent logic for an SRAM device
US6762973B2 · kind B2 · utility
2Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.