Framer method architecture and circuit with programmable symbol selection
US6763036B1 · kind B1 · utility
3Cited by
18References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1999 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Mar 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.