Security on hardware loops
US6763453B2 · kind B2 · utility
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4References
46Claims
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Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jan 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.