Data processor
US6763481B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle, in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes second arithmetic unit and comparator. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. The comparator compares the first result, transferred through the signal path in the idle cycle, to the second result and outputs a comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.