Physically defined varactor in a CMOS process
US6764891B2 · kind B2 · utility
3Cited by
1References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Aug 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.