Differential nor memory cell having two floating gate transistors
US6765825B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2003 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Mar 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM memory cell that includes two floating gate transistors. Each of the drain terminals of the transistors is coupled to a corresponding differential bit line. The source terminal of both transistors are coupled to a common current source or sink. Each of the control gate terminals are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control terminal is connected to. The floating gate transistor may be five-terminal devices that include an additional well terminal. In that case, a different set of bit lines is used to program the EEPROM memory cell as are used to read the EEPROM memory cell. While the drain terminals are coupled to the differential read bit lines, each of the well terminals is coupled to a corresponding differential program bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.