Offset mode phase locked loop frequency synthesizer with reduced divide ratio
US6765977B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) frequency synthesizer includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal, a frequency offset circuit including a mixer accepting the VCO frequency signal and a signal from a second oscillator to produce a shifted-frequency signal having a frequency significantly lower than the VCO output frequency, a programmable divider accepting the shifted-frequency signal and dividing the frequency of the shifted-frequency signal by a settable amount, a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; and a loop filter to filter a function of the phase difference to produce a control input to the VCO. The offset circuit shifts down the frequency without increasing the divide ratio of the loop as would a prescaler achieving the same frequency conversion as the frequency offset circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.