Processor with a general register set that includes address translation registers
US6766435B1 · kind B1 · utility
5Cited by
10References
20Claims
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Key dates
| Filing date | May 31, 2000 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | May 7, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.