Hardware loops
US6766444B1 · kind B1 · utility
6Cited by
7References
26Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Oct 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable processor is arranged to include early registers to support hardware loops. In this manner, a system may increase processing speed without significantly increasing power consumption. Loop conditions of a loop may be loaded into a set of early registers. These conditions may then be detected from the early registers before the loop conditions are written to a set of architectural registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.