Apparatus and methods for identifying bus protocol violations
US6766479B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Oct 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a novel structure and process for detecting protocol errors on a communications bus. According to one aspect of the invention, a protocol error detector comprises a physical error detector, a sequential error detector, and a logical error detector, each detecting physical, sequential, and logical protocol violations, respectively, and signaling a bus transaction error when a protocol violation is detected. In one embodiment, the protocol error detector substantially simultaneously checks each bus transaction for physical, sequential, and logical protocol violations. In another embodiment, the protocol error detector signals a detected bus transaction protocol violation substantially coincident with the bus transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.