Detection of AIOx ears for process control in FeRAM processing
US6767750B2 · kind B2 · utility
5Cited by
12References
16Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 3, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Dec 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.