Tapered threshold reset FET for CMOS imagers
US6768149B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Oct 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
Abstract
A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.