Packaged microchip with isolation
US6768196B2 · kind B2 · utility
32Cited by
14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged microchip has a stress sensitive microchip having a microchip coefficient of thermal expansion, a package having a package coefficient of thermal expansion, and an isolator having an isolator coefficient of thermal expansion. The isolator is connected between the stress sensitive microchip and the package. The microchip coefficient of thermal expansion illustratively is closer to the isolator coefficient of thermal expansion than it is to the package coefficient of thermal expansion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.