Apparatus and a method for pMOS drain current degradation compensation
US6768351B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Mar 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An apparatus and a method for compensating the drain current degradation in pMOS transistors are disclosed. The pMOS transistor receiving drain current compensation is a primary pMOS transistor. The apparatus comprises of a plurality of pMOS transistors subject to drain current degradation correlating to drain current degradation of the primary pMOS transistor, at least one compensation pMOS transistor coupled in parallel with the primary pMOS transistor, and an output voltage decoder to activate one or more of the compensation pMOS transistors to compensate for the drain current degradation of the primary pMOS transistor based on monitored drain current degradation of the plurality of pMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.