Phase locked loop fast power up methods and apparatus
US6768358B2 · kind B2 · utility
17Cited by
9References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by ensuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.