Fail-safe zero delay buffer with automatic internal reference
US6768362B1 · kind B1 · utility
6Cited by
33References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2001 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Aug 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.