Threshold voltage compensation
US6768369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | May 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A threshold voltage compensation method and circuit compensates a bias voltage applied to a transistor gate to account for variations in the transistors threshold voltage. In one embodiment, a logic stack includes three transistors in series between a high voltage source and ground with a higt voltage output between the first and second transistor and a full swing output between the second transistor and the third transistor. A bias voltage is applied to the gate of the second transistor to provide a minimum voltage level for the high voltage output. As the threshold voltage of the second transistor varies, the bias voltage is adjusted to compensate for the threshold voltage level variance and maintain the minimum voltage level for the higt voltage output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.