Intelligent phase lock loop
US6768385B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Aug 2, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL architecture with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery. The invention is particularly well suited for use in a video graphics a/d conversion circuit. An intelligent phase lock loop is optimized to determine the time difference between the closest rising edge of an PLL output signal and the rising edge of an input signal. The time difference in combination with the current PLL lock state determine an operational code used in a digital signal processing loop filter used to control a digitally controlled oscillator. The PLL also provides a stable output frequency during freerun periods, and a phase booster circuit for post-freerun fast phase recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.