Checkerboard buffer using more than two memory devices
US6768490B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0132
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for storing and retrieving data in parallel but in different orders, using three or more memory devices. In one implementation, data for pixels is stored according to a checkered pattern, sequentially among memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least three memory devices each having memory locations, where data is stored in parallel to and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, the second data switch controls providing data to the data destination according to the second order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.