Memory access in a computer system having parallel execution pipelines
US6769049B1 · kind B1 · utility
9Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2000 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | May 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory access controller receives load and store requests from a plurality of parallel execution pipelines and forms queues of store and load addresses. A comparator compares load addresses with store addresses in a store address queue and selects a store before load if an address match is found, but selects a load before a store if no address match is found.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.