Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load
US6769104B2 · kind B2 · utility
17Cited by
12References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | May 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing clock skew in a balanced tree when interfacing to an unbalanced load is presented. Unused portions of the balanced tree are replaced by a loading equivalent circuit to create a physically balanced load. In the preferred embodiment, the loading equivalent circuit is implemented with a single-pole resistor-capacitor circuit that has been modeled to match the RC characteristics of the replaced branch of the tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.