Charge carrier extracting transistor
US6770902B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/87
Abstract
An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.