High performance capacitor
US6770969B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Feb 13, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.