High speed tester with narrow output pulses
US6771061B2 · kind B2 · utility
15Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.