Programmable delay for processor control signals
US6771106B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 17, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing requirements. Circuit (100) includes a programmable delay chain (102) connected to a hysteresis circuit (150). A processor control signal is fed into the programmable delay chain (102) which includes at least one switch (104-116) and at least one resistive element (118-126) connected together. A first feedback circuit (128) connects the output of the programmable delay chain (102) to the input (IN2) of the first embodiment (100) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit (150) which provides a stable signal connects to an output driver (180) for driving the processor control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.