Semiconductor memory device and control method
US6771552B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2003 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device in which a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data are used to control operations for reading and writing data, the transmission of write data from FIFO memories to write amplifiers is controlled by the data strobe signal. In addition, switches for connecting write amplifiers with bit lines that are linked to memory cells that correspond to addresses to which write data are to be written are driven without delaying with respect to a timing signal that is synchronized with the system clock. Write data that have been received as burst input are transmitted in parallel from the FIFO memories to the write amplifiers in units of the prefetch number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.