Method and apparatus for remote memory clock synchronization for optimized leadoff performance
US6771669B1 · kind B1 · utility
0Cited by
3References
25Claims
0Family size
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Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.