Parallel greater than analysis method and apparatus
US6772187B1 · kind B1 · utility
4Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an apparatus and method for determining if a first number is greater than or equal to a second number. By analyzing nibbles of a multi-bit number in parallel to determine for each nibble if the nibbles are unequal and if a first nibble is greater than a second nibble and thereafter logically determining which of the highest order nibbles, if any, are unequal to discover whether the first number is greater than the second number, or determining that all nibble pairs are equal and thus concluding that both numbers are equal. A digital logic circuit is preferably employed for such analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.